The present invention relates to a memory access control apparatus and, more particularly, to a memory access control apparatus wherein block read processing is improved.
FIGS. 1A and 1B show an example of a conventional memory access control apparatus.
Referring to FIGS. 1A and 1B, a request reception port section (to be referred to as a port A hereinafter) 100 encircled by a broken line receives a request from a unit A and outputs data about a request address, request code, and intra-block address to a selector 200. The selector 200 also receives outputs from ports B and C that receive requests from units B and C, respectively, and have the same configurations as that of the port A. The selector 200 is connected to a busy check circuit 900 for checking availability of the units A, B, and C. The busy check circuit 900 performs busy check of the requests from the units A, B, and C, and outputs a selection signal 901 for selecting the unit A, B, or C that has passed the busy check to the selector 200 and a unit available signal 902 indicating that the unit A, B, or C is available to the corresponding port A, B, or C.
An output from the selector 200 is input to a request processing section 300 for processing a selected request. The request processing section 300 has a buffer memory 301. The processing section 300 is connected to a main memory unit (MMU) 400 by an MMU access line 302 for accessing the MMU 400 and an MMU reply line 401 for transmitting a reply from the MMU 400. An output from the processing section 300 is connected to reply registers 501, 502, and 503 corresponding to the units A, B, and C, respectively.
The selector 200, the request processing section 300, the main memory unit 400, and the reply registers 501 to 503 constitute a pipe line processing section.
The port A 100 comprises a unit A request reception buffer (to be referred to as a buffer hereinafter) 101 connected to the unit A, a buffer read register 102 connected to the output of the buffer 101, a buffer address register 103 for supplying an address to the buffer 101, a block read counter 104, an adder 105, a buffer read control circuit 106, and an AND gate 108.
The port A 100 operates in the following manner.
A request supplied from the unit A to the buffer 101 includes read, write, and block read requests. In the block read request, one block consists of 64 bytes (B) which are decomposed to eight 8-bytes read requests (to be referred to as 8B read requests). When a single block read request is supplied, the buffer read register 102 performs reading from the buffer 101 eight times.
The read address of the buffer 101 is supplied from the buffer read address register 103. When the request is a block read request, the content of the buffer read address register 103 does not change until read operation in response to one block read request is completed and is updated when readout in response to the 8th 8B read request is finished. When the request is a request other than the block read request, the content of the buffer read address register 103 is updated every time read access to the buffer 102 is performed.
The block read counter 104 has a value of 0 to 7 and counts eight 8B read requests in the case of a block read request. Therefore, the content of the counter 104 is always "0" at the start of the block reading.
The adder 105 adds an output representing the intra-block address of the buffer 101 and an output from the block read counter 104, and supplies the obtained sum to a corresponding bit position of the buffer read register 102. The buffer read control circuit 106 receives an output supplied from the buffer 101 to the buffer read register 102 and an output from the block read counter 104, and outputs an update signal 109 for the buffer read address register 103 and a valid signal 107 representing a block read request.
The buffer read control circuit 106 controls read operation of the buffer 101 in the following manner.
(1) When the request is other than a block read request, the update signal 109 becomes "1" every time read access to the buffer 101 is performed and the valid signal 107 becomes "0". As a result, the intra-block address in the buffer 101 is read out unchanged.
(2) When the request is a block read request, the valid signal 107 is set "1", and an output from the block read counter 104 is supplied to the adder 105 through the AND gate 108. Only when the output from the block read counter 104 is "7" and read access to the buffer 101 is performed in response to an 8B read request, the update signal 109 is set "1" so as to update the intra-block address 8 times.
When the unit A is selected by the selector 200, the request processing section 300 processes the request supplied from the port A 100. When data is not registered (to be referred to as a "miss" hereinafter) in the buffer memory 301, the request processing section 300 performs MMU access to the main memory unit 400, and in response the main memory unit 400 supplies block data to the buffer memory 301 by an MMU reply.
In the case of a block read request, when a hit has occurred, that is, when a miss has not occurred, the port A 100 outputs an 8B read request to the request processing section 300 eight times. The request processing section 300 processes the eight 8B read requests and sends reply data 8 times to the unit A that has supplied the request.
When a miss has occurred during a block read operation, the request processing section 300 sends a block read request to the main memory unit 400 by MMU access, and in response the main memory 400 registers 64B data in the buffer memory 301 by MMU reply. The request processing section 300 sends the reply data which is a first 8B data of the block to the unit A. The port A 100 outputs the remaining 8B read requests to the request processing section 300.
As described above, in conventional block read request processing, when a miss has occurred, reply data is supplied to a unit that has supplied the request and simultaneously data is registered in the buffer memory 301 of the request processing section 300. In such a conventional method, when a miss has occurred during a block read operation, all the reply data can be sent to a unit that has sent the request at once. However, since the block read request is executed as eight 8B read requests irrespective of occurrence of a hit or miss, wasteful processing is performed when a miss has occurred, resulting in a poor performance.